Field of the Invention
Discussion of the Background
A method has heretofore has been adopted, in which in order to relieve errors of semiconductor memories, spare row and column lines are additionally provided previously and the errors of the semiconductor memories are relieved by replacing row or column lines of defect memory cells regarded as faulty ones because of their errors.
The foregoing conventional method requires the semiconductor memory to provide the spare lines, resulting in a problem of a large chip size. In order to replace the row and column lines of the faulty memory cell with the spare line, it is necessary to write programs using fuses when a wafer test is conducted, and testing equipment for it is needed. Moreover, since there is sometimes a case where excessive processes must be conducted for an element for the fuse, leading to an increase in manufacturing cost. Besides the foregoing spare memory, as a error relief technology, there are also memory using an ECC (Error Checking and Correcting) technology, in which erroneous data is replaced with corrected data even when errors exist. This memory with ECC involves a problem that it has a memory capacitance larger than an original capacitance and has a large size chip because of addition of an ECC circuit. For example, in case of a 16M memory, the memory capacitance increases by 11 to 12%.